As is well known, electronic devices of the kind of devices that include non-volatile memory circuits, are normally supplied with relatively low voltages, on the order of a few volts. Reference will be made specifically to integrated circuits on a substrate of semiconductor material, usually of monocrystalline silicon. It is frequently necessary, however, that such devices be able to withstand higher working voltages than usually borne.
In fact, on one hand in some applications certain circuit portions are subjected to predetermined voltages, either external or generated within the device, which are relatively high. In the instance of non-volatile memory circuits, such as EPROM, FLASH or EEPROM memories, for example the memory cells programming voltages may attain values on the order of several times the supply voltage value.
On the other hand, instantaneous overvoltages of very high values, or electrostatic discharges--typically at the device terminals for connection with the outside, i.e. at the interconnection pins provided in the package encapsulating the device--may occur incidentally. Such occurrences can affect the circuit elements located in close proximity of the interconnections. In all of the above cases, the circuit elements of the device are required to operate properly and not be damaged.
As those skilled in the art know well, whereas in the presence of definitely high voltages, on the order of a few tens of volts and up to a few hundred volts, additional protection structures such as "field plates" are formed at the involved transistors. With relatively lower high voltages, such as those under specific consideration herein, no additional protection structures are provided, rather such circuit elements themselves that are more directly affected are formed using specific techniques for high voltages.
Particularly MOS transistors, whether of the P-channel or N-channel type, capable of withstanding high voltages, commonly have a suitably modified structure compared to a standard type of MOS transistor. Commonly and in the present invention, transistors for high voltages, capable of withstanding up to a few tens of volts, are made using conventional processes of the CMOS (Complementary MOS) type, which allow N-channel and P-channel MOS transistors to be formed simultaneously. In the instance of non-volatile memory circuits, the process may be arranged such that memory cell arrays are also formed in the same circuit. In this case, the MOS transistors may either be, for example, selection transistors internal of the array or external circuitry transistors, and moreover, the cell element itself is a MOS transistor of the floating gate type.
To fully appreciate the invention objects, first the structure of a standard MOS transistor should be held in mind, that is, a transistor structure which can withstand relatively low voltages not definitely exceeding the supply voltage, similar to each of the transistors that make up the CMOS pair. The transistor comprises an active region of source and an active region of drain which are formed, by implantation, directly in the substrate, or alternatively, in an N-well for P-channel transistors and in a P-well (or P-tub) for N-channel transistors. The two active regions, which are homogeneous and similarly doped, extend from one of the major surfaces of the chip of semiconductor material and have opposite polarity from that of the substrate or the well in which they are formed. An intermediate channel region separates the source and drain active regions, which are disposed symmetrically about the channel region. A gate consisting of one or two polysilicon layers, according to the technology used, is disposed over the substrate and separated from the latter by a relatively thin layer of gate oxide, thereby to overlie at least the channel region.
The gate polysilicon functions as a conductor, and is contacted at the top by a metallic layer, or gate electrode. For this purpose, the polysilicon is doped to enhance its conductivity, and usually has polarity of the N type, as is the case, for instance, in memory circuit applications. It should be further considered that in standard MOS transistors, both source and drain active regions have regular shapes, substantially rectangular in cross-section along the source-to-drain line.
On the contrary, transistors for relatively high voltages in CMOS processes usually have certain features that characterize and distinguish them from the standard ones just described. First of all, their source and drain active regions--and the latter especially--are arranged to form so-called gradually doped or graded junctions. That is, the junctions are formed such that the dopant concentration increases gradually from the edge of the channel region toward the contacts of the source and drain regions. This allows high breakdown voltages to be achieved for such junctions.
This taper in the diffused source and drain regions can be obtained by different techniques to provide different implant profiles. One of the commonest techniques for forming such regions is known as the LDD technique, and includes a further implantation being carried out at a relatively low dosage in the proximity of the channel region.
Sometimes the structure includes, in particular, a low-concentration doping of the drain junction in the proximity of the gate, to form the so-called drain extension which allows the electric field to be limited to within the area between the gate and the drain region. Accordingly, the working voltage range that the transistor can withstand is expanded without the gate oxide between the drain and the gate being ruptured by the injection of high-energy electrons into the gate oxide from the channel region.
A second structural feature of transistors for high voltages is the provision of gate oxides of much greater thickness (approximately 50% thicker) than the standard thickness, i.e. the so-called high-voltage oxides. In this way, it can be ensured that such an oxide of increased thickness will withstand applied voltages of even a much higher value than the integrated circuit supply voltage. The above technique, while being widely practiced, has certain limitations where still higher voltages are to be tolerated.
To make MOS transistors resistant to pulsed high voltages, such as in the case of transistors which are to provide protection against electrostatic discharges, in another prior art technique, the integrated structure of the transistor is altered to make it "stronger". Specifically, the drain region, which is formed in a suitable well having a low dopant concentration, can be regarded as theoretically split into three sub-regions: the drain in the typical sense of the word which consists of a layer with a high dopant concentration; a portion of the well itself; and a side portion of the well under the gate oxide, which also has a low dopant concentration. Provided between the last-mentioned portion and the drain is an insulation layer covered by an insulating oxide layer which is partly overlaid by the gate electrode and having a dopant concentration of an intermediate level to the drain and the well concentrations. Such transistor structures, while being effective even at high voltages, are nevertheless fairly complicated, and unlike the CMOS transistors described above, cannot be conveniently formed using standard techniques.
The underlying technical problem of the present invention is to provide a MOS transistor for high voltages, illustratively of up to a few tens of volts, which can function as a protection against electrostatic discharges, and which has such structural features that it can be made with a standard technology, in particular a CMOS technology. Another problem of the invention is to provide a MOS transistor which is compatible with the manufacturing processes for non-volatile memories, e.g. FLASH, EPROM and EEPROM memories.